1. Field of the Invention
The present invention relates to a semiconductor device having a circuit for separating a clock signal for a delay test.
2. Description of the Related Art
In recent years, a high speed operation is aimed in the semiconductor circuit, and a trouble caused due to a delay has increased. For accurate delay test, it is necessary to set many values to a circuit. Also, in order to accomplish a high trouble detection rate, it is necessary to increase the number of test patterns, namely, to increase a test time. As one method of reducing the number of the patterns in the delay test, a last-shift method is known in which a last clock signal during a shifting operation is used. When this last-shift method is applied to an LSSD (Level-Sensitive Scan Design) method in which a shifting operation is carried out in a two-phase clock signal, there is a problem of skew between pins of a tester. Thus, when the last-shift method is applied to the LSSD method, it is difficult to test a semiconductor device in a high frequency of 100 MHz or more.
As a conventional technique on a scan test, a semiconductor device is known in Japanese Laid Open Patent Publication (JP-P2002-289776A), in which a scan test circuit is installed. This conventional semiconductor device includes a scan test circuit, a clock signal generating circuit and a selector. The scan test circuit has a plurality of flip-flops and has a capture mode and a shift mode. In the capture mode, a plurality of data from an internal circuit are captured into the plurality of flip-flops in parallel in synchronization with a clock signal. In the shift mode, data held by the plurality of flip-flops as a scan chain are shifted in synchronization with the clock signal. The clock signal generating circuit generates a clock signal in synchronization with an external clock signal. The selector receives two clock signals, selects one of the two clock signals in accordance with a scan enable signal for switching between the shift mode and the capture mode, and sends the selected clock signal to clock input terminals of the plurality of flip-flops.
The conventional semiconductor device will be described below with reference to FIG. 1. As shown in FIG. 1, an MUX method in which the shifting operation is carried out in a single-phase clock signal. The conventional semiconductor device is provided with a scan test circuit 1, a selector circuit 2, a clock signal generating circuit 3 and an internal circuit 4 as a scan test target. The operation of the delay test based on the last-shift method is well known, and therefore it will be described briefly. The delay test of the internal circuit 4 is carried out by giving a time difference between a last clock signal in the shift mode and the clock signal in the capture mode to the scan test circuit 1 at the timing of an actual operation. The selector 2 receives a clock signal CLK, a clock signal generated by the clock signal generating circuit 3 and a scan enable signal for switching the scan test circuit 1 to the shift mode or capture mode.
As shown in FIGS. 2A to 2D, by using the clock signal generating circuit 3, it is possible to generate one period Tc of the clock signal in the actual operation shorter than one period Ts of the clock signal used in the shifting operation by the internal circuit 4. In this way, the clock signal is generated in the actual operation speed only during the last-shift operation by the internal circuit 4.
However, in the conventional semiconductor device, the clock signal is made faster by using the internal circuit. Therefore, when the clock signal Tc of a higher rate should be supplied, the frequency of the clock signal Ts in the shift mode is also increased. Thus, the supply of the clock signal of an excessively higher rate results in a problem that the shifting operation becomes impossible. That is, in the conventional example, the test frequency of the delay test is limited by the design.